Design and Implementation of High Speed 16x16 CMOS Vedic Multiplier
( Vol-3,Issue-3,May 2018 )

MLA

Praveen Kumar Sharma, Gajendra Sujediya et al."Design and Implementation of High Speed 16x16 CMOS Vedic Multiplier". International Journal of Electrical , Electronics and Computers(ISSN: 2456-2319),vol 3, no. 3, 2018, pp.07-11 Infogain Publication doi:10.22161/eec.3.3.2

APA

Praveen Kumar Sharma, Gajendra Sujediya, P.(2018).Design and Implementation of High Speed 16x16 CMOS Vedic Multiplier. International Journal of Electrical , Electronics and Computers(ISSN: 2456-2319).3(3), 07-11.10.22161/eec.3.3.2

Chicago

Praveen Kumar Sharma, Gajendra Sujediya, P.(2018).Design and Implementation of High Speed 16x16 CMOS Vedic Multiplier. International Journal of Electrical , Electronics and Computers(ISSN: 2456-2319).3(3), pp.07-11.

Harvard

Praveen Kumar Sharma, Gajendra Sujediya. 2018."Design and Implementation of High Speed 16x16 CMOS Vedic Multiplier". International Journal of Electrical , Electronics and Computers(ISSN: 2456-2319).3(3):07-11.Doi:10.22161/eec.3.3.2

IEEE

Praveen Kumar Sharma, Gajendra Sujediya."Design and Implementation of High Speed 16x16 CMOS Vedic Multiplier", International Journal of Electrical , Electronics and Computers(ISSN: 2456-2319),vol.3,no. 3, pp.07-11,2018.

Bibtex

@article { praveenkumarsharma2018design,
title={Design and Implementation of High Speed 16x16 CMOS Vedic Multiplier},
author={Praveen Kumar Sharma, Gajendra Sujediya , R},
journal={International Journal of Electrical , Electronics and Computers},
volume={3},
year= {2018} ,
}