Design and Implementation of High Speed 16x16 CMOS Vedic Multiplier

Design and Implementation of High Speed 16x16 CMOS Vedic Multiplier ( Vol-3,Issue-3,May - June 2018 )

Author: Praveen Kumar Sharma, Gajendra Sujediya

Keyword: Multiplier, Vedic Mathematics, CMOS, 16x16 multiplier.

Abstract: In today scenario digital circuits are become more and more complex because of long arithmetic calculations but with the help of Vedic mathematics that calculations can become easy and fast. To make multiplier we have different techniques, in this paper we design 16x16 CMOS multiplier using Vedic mathematics technique.

References:

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