Design and Implementation of High Speed 16x16 CMOS Vedic Multiplier

In today scenario digital circuits are become more and more complex because of long arithmetic calculations but with the help of Vedic mathematics that calculations can become easy and fast. To make multiplier we have different techniques, in this paper we design 16x16 CMOS multiplier using Vedic mathematics technique. Keywords—Multiplier, Vedic Mathematics, CMOS, 16x16 multiplier.


INTRODUCTION
The word 'Vedic' is derived from the word 'Veda' which means the store-house of all knowledge. Vedic mathematics is mainly based on 16 Sutras (or aphorisms) dealing with various branches of mathematics like arithmetic, algebra, geometry etc. In this paper, Urdhva Tiryakbhyam Sutra is first applied to the binary number system and is used to develop digital multiplier architecture. This is shown to be very similar to the popular array multiplier architecture. This Sutra also shows the effectiveness of to reduce the NXN multiplier structure into an efficient 4X4 multiplier structures. The Multiplier Architecture is based on the Vertical and Crosswise algorithm of ancient Indian Vedic Mathematics. Urdhva tiryakbhyam Sutra is most efficient Sutra (Algorithm) for high speed multiplication, and less number of transistor count. An adiabatic logic is used to design 16X16 CMOS Vedic multiplier [1].

II.
BASIC OF VEDIC MULTIPLIER The Vedic mathematics is part of four Vedas (books of wisdom). It is part of Sthapatya-Veda (book on civil engineering and architecture), which is an upa-veda (supplement) of Atharva Veda. It covers explanation of several modern mathematical terms including arithmetic, geometry (plane, co-ordinate), trigonometry, quadratic equations, factorization and even calculus. The beauty of Vedic mathematics lies in the fact that it reduces the otherwise cumbersome-looking calculations in conventional mathematics to a very simple one [2]. This is so because the Vedic formulae are claimed to be based on the natural principles on which the human mind works.

III. DESIGN AND IMPLEMENTATION OF VEDIC MULTIPLIER
The designing of Vedic Multiplier is based on a novel technique of digital multiplication which is quite different from the conventional method of multiplication like add and shift. Where small blocks are used to design the bigger one.

AND Gate
The AND gate is a basic digital logic gate that implements logical conjunction it behaves according to the truth table to the right. A HIGH output (1) results only if both the inputs to the AND gate are HIGH (1). If neither or only one input to the AND gate is HIGH, a LOW output results.

XOR Gate
The XOR gate performs an exclusive -OR operation on the inputs. Exclusive -OR produces a 1 output if one (but only one) input is 1. If both operands are 0, the output is 0. Likewise, if both operands are 1, the output is also 0.

Design of 4x4 Vedic Multiplier
Let's analyze 4x4 multiplications [3], say A3A2A1A0 and B3B2B1B0. Following are the output line for the multiplication result, Q7Q6Q5Q4Q3Q2Q1Q0 [4]. Block diagram of 4x4 Vedic Multiplier is given below

Design of 8x8 Vedic Multiplier
Now the basic building block of 8x8 bit Vedic multiplier is 4x4 bits multiplier. For bigger multiplier implementation like 8x8 bits 5multiplier the 4x4 bits multiplier units has been used as components which are implemented already in Tanner library [5]. The structural modeling of any design shows fastest design.

Design of 16x16 Vedic Multiplier
The 16X16 bit multiplier structured using 8X8 bits blocks as shown below. The 16 bit multiplicand A can be decomposed into pair of 8 bits AH-AL. Similarly multiplicand B can be decomposed into BH-BL [6]. The outputs of 8X8 bit multipliers are added accordingly to obtain the 32 bits final product. Thus, in the final stage two adders are also required. Similarly, we have extended same for input bits 32, 64.  /dx.doi.org/10.22161/eec.3.3.2  ISSN: 2456-2319 www.eecjournal.com Page | 9 multiplier is designed by means of 180nm CMOS technology.

VI. CONCLUSION
The design of 16x16 CMOS Vedic multiplier has been implemented on Tanner EDA tool 13.00v. The computation delay for 8x8 bits Vedic multiplier is 9.203 ns at 5V and for 16x16 CMOS Vedic multiplier is 9.087 ns at 5V. Since power and delay of proposed Vedic multiplier is reduced as compared to existing multiplier. Thus, it is more efficient for fast multiplication.